SPI Data Receive Register - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

The SPI Data Receive Register (SPI DRR) is used to read data that is received from the SPI bus. This is a double-buffered register. The received data is placed in this register after each complete transfer. The SPI architecture does not provide any means for a slave to throttle traffic on the bus; consequently, the SPI DRR is updated following each completed transaction only if the SPI DRR was read prior to the last SPI transfer.

If the SPI DRR was not read and is full, the most recently transferred data is lost and a receive overrun interrupt occurs. The same condition can also occur with a master SPI device.

The choice of inclusion (FIFO Depth = 16 or 256) or exclusion (FIFO Depth = 0) of the FIFO in the design is available only when the core is configured in standard SPI mode. When the core is configured in dual or quad SPI mode, the FIFO always exists. In this mode, the FIFO depth is defined with the parameter FIFO Depth (allowed values are 16 or 256). For both master and slave SPI configuration mode of the core (in Standard SPI mode only) with a receive FIFO, the data is buffered in the FIFO. The receive FIFO is a read-only buffer. If an attempt is made to read an empty receive register or FIFO, it gives out an error in the Status register. Writes to the SPI DRR do not modify the register contents and return with a successful OK response.

The power-on reset values for the SPI DRR are unknown. When known data has been written into the receive FIFO during core transactions, the data in this register can be considered for reading. The SPI DRR is shown in This Figure, while the specifics of the data format is described Table: SPI Data Receive Register Description (Core Base Address + 0x6C).


IMPORTANT:   Based on the command that is issued to the SPI device, a certain unwanted number of bytes are written to the Receive FIFO. These bytes have to be discarded.

Figure 2-5:      SPI Data Receive Register (Core Base Address + 0x6C)

X-Ref Target - Figure 2-5

Table 2-8:      SPI Data Receive Register Description (Core Base Address + 0x6C)



Core Access

Reset Value



RX Data(1) (DN-1 - D0)

Read only


N-bit SPI receive data. N can be 8, 16 or 32.(2)

N = 8 when the Transfer Width parameter is 8.
N = 16 when the Transfer Width parameter is 16.
N = 32 when the Transfer Width parameter is 32.


1.The DN-1 bit always represents the MSB bit irrespective of LSB first or MSB first transfer selection. When the Transfer Width parameter is 8 or 16, the unused upper bits ((AXI data width – 1) to N) are reserved.

2.In standard SPI mode, the width of this register can be 8 or 16 or 32 based on the core configuration. In dual or quad SPI mode, this register is 8-bit wide.

3.In standard mode, reading an empty DRR FIFO returns a slave error.