SPI Master Device with/without FIFOs and Slave Select Vector Asserted Manually Using SPICR Bit 7 - 3.2 English

PG153 AXI Quad SPI Product Guide

Document ID
Release Date
3.2 English

This flow permits the transfer of N number of byte/half-word/word elements with a single toggling of the slave select vector. This is the default mode of operation. Use these steps to successfully complete the SPI transaction:

1.Start from a known state, including SPI bus arbitration.

2.Configure DGIER and IPIER registers as required.

3.Configure the target slave SPI device as required. This includes configuration of the DTR and control register of the slave SPI core as well as enabling it.

4.Write initial data to the master SPI DTR register/FIFO. This assumes that the SPI master is disabled.

a.In Legacy mode, the AXI4-Lite transactions are written to the DTR one at a time.

b.In Enhanced mode, the AXI4 interface must generate a FIXED burst transaction only. An INCR transaction with length 0 is acceptable but if the INCR burst is targeted at the FIFO locations (DTR or DRR), the core behavior is not guaranteed. The INCR transactions are treated as FIXED transactions. To avoid FIFO overflow or underflow errors, The transmit or receive occupancy register should be read before initiating a burst of any length. The maximum burst length for read command to DRR supported in non-XIP mode is 16 or the occupancy value of the Rx FIFO, whichever is lower. The core behavior is not guaranteed otherwise. In case of writing to DTR register, the core behavior guaranteed only if a write length is less than or equal to FIFO_Depth - DTR occupancy value.

5.Ensure the SPISSR register contains all ones.

6.Write configuration data to the master SPI device SPICR as required, including setting bit 7 for manual assertion of the SS vector and setting both enable and master transfer inhibit bits. This initializes SCK and IO0 but inhibits transfer.

7.Write to the SPISSR register to manually assert the SS vector.

8.Write the preceding configuration data to the master SPI device SPICR register, but clear the inhibit bit which starts the transfer.

9.Wait for an interrupt (typically IPISR bit 4) or poll status for completion. The wait time depends on the SPI clock ratio.

10.Set the master transaction inhibit bit to service the interrupt request.

11.Write new data to the master register/FIFOs and slave devices.

12.Clear the master transaction inhibit bit to continue the N 8-bit element transfer.

Note:   An overrun of the SPI DRR register/FIFO can occur if the SPI DRR register/FIFOs are not read properly. Also, SCK has stretched the idle levels between element transfers (or groups of element transfers if using FIFOs) and that IO0 can transition at the end of an element transfer (or group of transfers), but it is stable for divide-by-2 clocking modes. IO0 is valid at the falling edge of SCK, and for all other modes, it is two ext_spi_clk cycles after the falling edge of SCK. Also there are no idle cycles between each new SPI transaction.

13.Repeat step 10 through step 12 until all data is transferred.

14.Write all ones to the SPISSR register or exit the manual slave select assert mode to deassert the SS vector while SCK and IO0 are in the idle state.

15.Disable devices as required.