AXI4-Lite Interface Functionality in Standard SPI Multi-Master Configuration - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)
Document ID
PG153
Release Date
2025-01-21
Version
3.2 English

The SPI bus to a given slave device (Nth device) consists of four wires:

  • Serial clock (SCK)
  • IO0 (Master out, slave in (MOSI))
  • IO1 (Master in, slave out (MISO))
  • Slave select (SS(N))

The signals SCK, IO0(MOSI), and IO1(MISO) are shared for all slaves and masters. See the following figure, where any one of the SPI devices can be configured as a master and the others can be configured as slaves (via register(60h) configuration). In such cases the master will drive the SPISEL pin of the slaves from the ss pins.

Figure 1. Multi-Master Configuration Block Diagram for Standard SPI Mode
Note: When the core is generated in master mode but through register configuration (60h) if it is configured as a slave, SPISEL should be driven to the core from the SPI master.

Each master SPI device has the functionality to generate an active-Low, one-hot encoded SS(N) vector where each bit is assigned an SS signal for each slave SPI device. It is possible for both SPI master/slave devices to be internal to the FPGA and SPI slave devices to be external to the FPGA. SPI pins are automatically generated through the AMD Vivado™ Design Suite when interfacing to an external SPI slave device. Multiple SPI master/slave devices are shown in the preceeding figure. The same configuration diagram is applicable for dual mode.