XIP Configuration Register - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

The bit assignments for the XIP Configuration Register (XIP-CR) are shown in This Figure. This register is used to configure the XIP (read-only) mode. This is a read/write register used to configure the CPOL and CPHA modes. In XIP mode, either CPOL–CPHA = 00 or CPOL–CPHA = 11 is supported. For any other combination the error flag is set in the status register and the transaction on the AXI4 interface is not accepted by the core. Before the start of any new AXI4 transaction, the core checks the CPOL and CPHA settings.

Figure 2-12:      XIP Configuration Register (Core Base Address+0x60)

X-Ref Target - Figure 2-12