Exceptions from the Motorola M68HC11-Rev. 4.0 Reference Manual - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

A slave mode-fault error is added to provide an interrupt if a SPI device is configured as a slave and is selected when not enabled.

In this design, the SPI DTR and SPI DRR registers have independent addresses. This is an exception to the M68HC11 specification that calls for two registers to have the same address.

All SS signals are required to be routed between SPI devices internally to the FPGA. This is because toggling of the SS signal is utilized in slaves to minimize FPGA resources.

Manual control of the SS signals is provided by setting Bit[7] in the SPICR register. When the device is configured as a master and is enabled while Bit[7] of the SPICR register is set, the vector in the SPISSR register is asserted. When this mode is enabled, multiple elements can be transferred without toggling the SS vector.

A control bit is provided to inhibit master transfers. This bit is effective in any master mode, but its primary intent is manual control of the SS signals.

In the M68HC11 implementation, the transmit register is transparent to the shift register which necessitates the write collision error (WCOL) detection hardware. This feature is not implemented in this design.

The interrupt enable bit (SPIE) defined by the M68HC11 specifications which resides in the M68HC11 control register has been moved to the IPIER register. In place of the SPIE bit, there is a bit to select local master loopback mode for testing.

An option is implemented in this design to implement FIFOs on both transmit and receive (Full Duplex only) mode.

M68HC11 implementation supports only byte transfer. In this design either a byte, half-word, or word transfer can be configured using the Transaction Width parameter.

The baud rate generator is specified by Motorola to be programmable using bits in the control register; however, in this FPGA design the baud rate generator is programmable using parameters in the VHDL implementation. Thus, run-time configuration of the baud rate is not possible. Beyond the ratios of 2, 4, 16 and 32, all integer multiples of 16 up to 2048 are allowed.

Most of the SPI slave devices support the SPI modes 0 and 3. For some of these devices, the data valid time of 8 ns from the falling edge of SCK is applicable. While operating with these devices at a higher speed of 50 MHz (most of the instructions support this speed), the core should be configured with Frequency Ratio set to 2 (where the AXI is configured to operate at 100 MHz).

Due to limited time availability in the design as well as real SPI slave behavior for data change, the data in the SPI core is registered in the middle of each SPI rising and next consecutive falling edge inside the core. This adds 5 ns of time to the core (while operating at 100 MHz on the ext_spi_clk port) for registering the data. As per the M68HC11 document, the master should register data on each rising edge of SCK in SPI modes 1 and 3. Note that the data registering mechanism when Frequency Ratio is 2 follows a different pattern than specified in the standard although this is applicable to the data registering mechanism in the core only. The SPI core, when configured in master mode, changes data on each falling edge and this behavior is as per the M68HC11 standard.

When the AXI Quad SPI core is configured in slave mode (Mode set to Standard), the data in the core is registered on the SCK rising edge + one AXI clock cycle. Internally, this data is registered on the next rising edge of the AXI clock cycle. The core changes the data on the SCK falling edge + one AXI clock cycle.

In Standard SPI mode of operation, when the SCK RATIO = 16 is used, the core provides approximately seven cycles of ext_spi_clk setup time for the downstream device to register the data on the next SPI rising edge.