Specification Exceptions - Specification Exceptions - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)

Document ID: PG153
Release Date: 2026-01-16
Version: 3.2 English

Introduction
Features
IP Facts
Overview
Legacy Mode
Standard SPI Mode
Dual/Quad SPI Mode
Common Information for Both SPI Modes
AXI4 Interface
Enhanced Mode
XIP Mode
Dual Quad SPI Mode
Core Internal Submodules
Enable Performance Mode Not Selected
AXI4-Lite Interface Module
SPI Register Module
Interrupt Controller Register Set Module
SPI Module
Optional FIFOs
STARTUPEn Module
Enable STARTUPE2 Primitive Parameter
Enable STARTUPE3 Primitive Parameter
Quad SPI Control Logic Module
Feature Summary
Unsupported Features
Licensing and Ordering
Product Specification
Standards
Performance
Resource Utilization
Port Descriptions
Register Space (Legacy and Enhanced Non-XIP Mode)
Register Details
Software Reset Register
SPI Control Register
SPI Status Register
SPI Data Transmit Register
Dual/Quad Mode
SPI Data Receive Register
SPI Slave Select Register
SPI Transmit FIFO Occupancy Register
SPI Receive FIFO Occupancy Register
Interrupt Register Set Description
Device Global Interrupt Enable Register
IP Interrupt Status Register (IPISR)
IP Interrupt Enable Register (IPIER)
XIP Mode
XIP Mode Commands
XIP Configuration Register
XIP Status Register
Specification Exceptions
Exceptions from the Motorola M68HC11-Rev. 4.0 Reference Manual
Other Exceptions
Designing with the Core
General Design Guidelines
Functionality Based on AXI Interfaces
AXI4-Lite Interface
AXI4 Interface (Enhanced Mode)
AXI4 Read-Only Interface (XIP Mode)
Standard SPI Device Features with Only AXI4-Lite Interface
AXI4-Lite Interface Functionality in Standard SPI Multi-Master Configuration
AXI4-Lite Interface Standard SPI Mode — Optional FIFOs in Legacy Mode
AXI4-Lite Interface Dual/Quad SPI Mode — Optional FIFO Depth
AXI4-Lite Interface SPI Master Loopback Operation
AXI4-Lite Interface Hardware Error Detection
Setting the Frequency Ratio Parameter
AXI4-Lite Interface SPI Slave Mode — Standard SPI Configuration in Legacy Mode Only
Using the Enable STARTUPEn Primitive Parameter
Enable STARTUPEn Primitive is Selected
Core Behavior and Ports
Using the Dual Quad Mode
Enable STARTUPEn Primitive is Not Selected
Core Behavior and Ports
Core Behavior in Legacy and Enhanced Non-XIP Mode
Core Behavior in XIP Mode
Winbond Memory
Micron Memory
Spansion Memory
Macronix Memory
Commonly Supported Commands for Dual SPI and Mixed Memory Mode
Commonly Supported Commands for Quad SPI and Mixed Memory Mode
XIP Mode Commands
Winbond Memory (Ex: W25Q64VSFIG)
Micron Memory (Ex: N25Q256)
Spansion Memory (Ex: S70FL01GS)
Macronix Memory (Ex: MX66U1G45G)
Clocking (SPI Clock Phase and Polarity Control)
Resets
Protocol Description
AXI Quad SPI Core Behavior in Legacy and Enhanced Mode
Mode = Dual
Slave Device = Mixed
Slave Device = Winbond
Slave Device = Micron
Slave Device = Spansion
Mode = Quad
Slave Device = Mixed
Slave Device = Winbond
Slave Device = Micron
Slave Device = Spansion
Core Behavior in XIP Mode
Standard SPI Mode Transactions
SPI Master Device with/without FIFOs and Slave Select Vector Asserted Manually Using SPICR Bit 7
SPI Master and Slave Devices without FIFOs Performing One 8-bit/16-bit/32-bit Transfer (Optional Mode)
SPI Master and Slave Devices Where Registers/FIFOs are Filled Before the SPI Transfer Begins and Multiple Discrete 8-bit Transfers are Performed (Optional Mode)
SPI Master and Slave Devices with FIFOs Where Some Initial Data is Written to FIFOs, the SPI Transfer is Started, Data is Written to the FIFOs as Fast or Faster than the SPI Transfer and Multiple Discrete 8-bit Transfers are Performed (Optional Mode).
Dual/Quad SPI Mode Transactions
Dual/Quad Mode SPI Configuration
Transfer Formats
CPHA Equals Zero Transfer Format
CPHA Equals One Transfer Format
SPI Protocol Slave Select Assertion Modes
SPI Protocol with Automatic Slave Select Assertion
SPI Protocol with Manual Slave Select Assertion
Beginning and Ending SPI Transfers
Transfer Begin Period
Transfer End Period
Design Flow Steps
Customizing and Generating the Core
AXI Interface Options
SPI Options
Remaining Options
User Parameters
Output Generation
Constraining the Core
Required Constraints
Write Operation to SPI
Read Operation
Constraining the IP
Constraints in Dual Quad Mode
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Example Design
Overview
Implementing the Example Design
Testing the Example Design on a KC705 Board
Legacy Mode and Performance Mode Example Design Behavior
XIP Mode Example Design Behavior
Simulating the Example Design
Setting Up the Simulation
Example Programming Sequence
Write Enable Command Sequence
Erase Command Sequence
Write Data Command Sequence
Read Data Command Sequence
Test Bench
Overview
Checking Results
Verification, Compliance, and Interoperability
Upgrading
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Hardware Debug
Interface Debug
AXI4-Lite Interfaces
AXI4 Interfaces
Enhanced Mode Debug
XIP Mode Debug
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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