AXI4 Interface (Enhanced Mode) - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

If the AXI4 interface is chosen, it is mandatory that all the registers are single-length access only. If burst is attempted (except for the SPI DTR or SPI DRR), the core behavior is not guaranteed. The SPI DTR and SPI DRR registers can be accessed as 32-bits. The FIXED burst is allowed only for the SPI DTR and SPI DRR registers. Out of 32 bits of FIXED burst, only 8 bits are valid. Read the occupancy registers before initiating the recursive FIXED burst. The occupancy registers provide the length of the FIXED burst to be performed. Only the last eight bits should be considered as actual data.

While carrying out the write burst operation in the DTR register, it is illegal to have holes in the write strobes. This is not allowed by the core and core behavior in this instance is not guaranteed.

When starting any new transaction at the SPI flash memory, the DTR FIFO should be always filled with a command followed by address, dummy bytes, then data bytes. This sequence should be strictly adhered to by the application. The read or write data occupancy registers indicate the number of locations left in the receive or transmit FIFO which help to determine the burst length of the next transaction. This mode is most suitable for CDMA-based applications.