The definition of the transfer beginning period for the AXI Quad SPI core is consistent with the M68HC11 reference manual. This manual can be referenced for more details. All SPI transfers are started and controlled by a master SPI device.
As a slave, the processor considers a transfer to begin
with the first SCK edge or the falling edge of SS̅
, depending on the CPHA
format selected. When CPHA equals zero, the falling edge of S̅S̅
indicates
the beginning of a transfer. When CPHA equals one, the first edge on the SCK indicates the
start of the transfer. In either CPHA format, a transfer can be aborted by de-asserting the
SS̅(N)
signal, which causes the SPI slave logic and bit counters to be
reset. In this implementation, the software driver can deselect all slaves (that is,
S̅S̅(N)
is driven High) to abort a transaction. Although the hardware is
capable of changing slaves during the middle of a single or burst transfer, the software
should be designed to prevent this.
In slave configuration, the data
is transmitted from the SPI DTR register on the first AXI rising
clock edge following SS
signal being
asserted. The data should be available in the register or FIFO. If
data is not available, then the underrun interrupt is asserted.