Write Operation to SPI - 3.2 English

PG153 AXI Quad SPI Product Guide

Document ID
PG153
Release Date
2022-04-26
Version
3.2 English

In SCK ratio = 2 scenarios, a successful write operation should be completed within two clock cycles of ext_spi_clk.

 

This means:

   The rising-edge of SCK must be between these two active edges of ext_spi_clk.

   The position of the rising-edge of SCK should be such that it meets the Tsetup and Thold time of the SPI device.

   Tsetup analysis should be done by taking into account the minimum delay on SCK (that is, the minimum delay of STARTUP), the maximum delay of the datapath, and the board routing delay.

   Similarly Thold analysis should be done by taking into account the maximum delay on SCK (that is, the maximum delay of STARTUP), the minimum delay of data, and the board routing delay.

This requirement of the SPI device further brings down the operational frequency of the IP.

Based on this you obtain two numbers. Fmax that will break Tsu and Fmax that will break Th:

Fmax2 = fn {STARTUP delay min, max datapath, board routing delay, Tsu}

Fmax3 = fn {STARTUP delay max, min datapath, board routing delay, Th}

The more restrictive number of the above two has to be considered.