The SPI Control Register (SPICR) allows programmer control over various aspects of the AXI Quad SPI core. The bit assignment in the SPICR is shown in the following figure and described in the following table.
Bits | Name | Core Access | Reset Value | Description |
---|---|---|---|---|
31:10 | Reserved | NA | NA | Reserved. |
9 | LSB First | R/W | 0 |
LSB first:(1) This bit selects LSB first data transfer format. The default transfer format is MSB first. When set to: 0 = MSB first transfer format. 1 = LSB first transfer format. Note: In Dual/Quad SPI mode, only the MSB first mode of the
core is allowed.
|
8 |
Master Transaction Inhibit |
R/W | 1 |
Master transaction inhibit: This bit inhibits master transactions. This bit has no effect on slave operation. When set to: 0 = Master transactions enabled. 1 = Master transactions disabled. Note: This bit immediately inhibits the transaction. Setting
this bit while transfer is in progress would result in unpredictable
outcome.
|
7 |
Manual Slave Select Assertion Enable |
R/W | 1 |
Manual slave select assertion enable: This bit forces the data in the slave select register to be asserted on the slave select output anytime the device is configured as a master and the device is enabled (SPE asserted). This bit has no effect on slave operation. When set to: 0 = Slave select output asserted by master core logic. 1 = Slave select output follows data in slave select register. Note: The manual slave assertion mode is supported in standard
SPI mode only. For more information see SPI Protocol Slave Select Assertion Modes.
|
6 | RX FIFO Reset | R/W | 0 |
Receive FIFO reset: When written to 1, this bit forces a reset of the receive FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0. When set to: 0 = Receive FIFO normal operation. 1 = Reset receive FIFO pointer. |
5 | TX FIFO Reset | R/W | 0 |
Transmit FIFO reset: When written to 1, this bit forces a reset of the transmit FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0. When set to: 0 = Transmit FIFO normal operation. 1 = Reset transmit FIFO pointer. |
4 | CPHA | R/W | 0 |
Clock phase:(2) Setting this bit selects one of two fundamentally different transfer formats. |
3 | CPOL | R/W | 0 |
Clock polarity:(2) Setting this bit defines clock polarity. When set to: 0 = Active-High clock; SCK idles Low. 1 = Active-Low clock; SCK idles High. |
2 | Master | R/W | 0 |
Master (SPI master mode):(3) Setting this bit configures the SPI device as a master or a slave. When set to: 0 = Slave configuration. 1 = Master configuration. Note: In dual/quad SPI mode only the master mode of the core is
allowed.
Standard Slave mode is not supported for SCK ratio = 2. |
1 | SPE | R/W | 0 |
SPI system enable: Setting this bit to 1 enables the SPI devices as noted here. When set to:
|
0 | LOOP | R/W | 0 |
Local loopback mode:(4) Enables local loopback operation and is functional only in standard SPI master mode. When set to:
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