SPI Control Register - 3.2 English

31:10

Reserved

NA

NA

Reserved.

9

LSB First

R/W

0

LSB first:⁽¹⁾

This bit selects LSB first data transfer format.
The default transfer format is MSB first.
When set to:
0 = MSB first transfer format.
1 = LSB first transfer format.

Note:   In Dual/Quad SPI mode, only the MSB first mode of the core is allowed.

8

Master
Transaction
Inhibit

R/W

1

Master transaction inhibit:

This bit inhibits master transactions.
This bit has no effect on slave operation.
When set to:
0 = Master transactions enabled.
1 = Master transactions disabled.

Note:   This bit immediately inhibits the transaction. Setting this bit while transfer is in progress would result in unpredictable outcome.

7

Manual Slave
Select
Assertion
Enable

R/W

1

Manual slave select assertion enable:

This bit forces the data in the slave select register to be asserted on the slave select output anytime the device is configured as a master and the device is enabled (SPE asserted).
This bit has no effect on slave operation.
When set to:
0 = Slave select output asserted by master core logic.
1 = Slave select output follows data in slave select register.

Note:   The manual slave assertion mode is supported in standard SPI mode only. For more information see SPI Protocol Slave Select Assertion Modes.

6

RX FIFO Reset

R/W

0

Receive FIFO reset:

When written to 1, this bit forces a reset of the receive FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0.
When set to:
0 = Receive FIFO normal operation.
1 = Reset receive FIFO pointer.

5

TX FIFO Reset

R/W

0

Transmit FIFO reset:

When written to 1, this bit forces a reset of the transmit FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0.
When set to:
0 = Transmit FIFO normal operation.
1 = Reset transmit FIFO pointer.

4

CPHA

R/W

0

Clock phase:⁽²⁾

Setting this bit selects one of two fundamentally different transfer formats.
See Clocking (SPI Clock Phase and Polarity Control).

3

CPOL

R/W

0

Clock polarity:⁽²⁾

Setting this bit defines clock polarity.
When set to:
0 = Active-High clock; SCK idles Low.
1 = Active-Low clock; SCK idles High.

2

Master

R/W

0

Master (SPI master mode):⁽³⁾

Setting this bit configures the SPI device as a master or a slave.
When set to:
0 = Slave configuration.
1 = Master configuration.

Note:   In dual/quad SPI mode only the master mode of the core is allowed.

Note:   Standard Slave mode is not supported for SCK ratio = 2.

1

SPE

R/W

0

SPI system enable:

Setting this bit to 1 enables the SPI devices as noted here.
When set to:

•0 = SPI system disabled. Both master and slave outputs are in 3-state and slave inputs are ignored.

•1 = SPI system enabled. Master outputs active (for example, IO0 (MOSI) and SCK in idle state) and slave outputs become active if SS becomes asserted. The master starts transferring when transmit data is available.

0

LOOP

R/W

0

Local loopback mode:⁽⁴⁾

Enables local loopback operation and is functional only in standard SPI master mode.
When set to:

•0 = Normal operation.

•1 = Loopback mode. The transmitter output is internally connected to the receiver input. The receiver and transmitter operate normally, except that received data (from remote slave) is ignored.

Notes:

1.Setting of this bit (LSB First) is allowed only in Standard SPI mode. Dual/quad SPI modes support MSB first mode only. In dual/quad SPI mode if this bit is set, the corresponding error bit is set in SPISR and an interrupt is generated.

2.In dual and quad SPI mode, values for CPHA-CPOL of either 00 or 11 are allowed. Setting of other configurations causes a malfunction while communicating with memory. If other values are set, the corresponding error bit is set in the SPISR and an interrupt is generated if the corresponding bit is enabled in the SPI IPIER register.

3.The slave mode support is available only in standard SPI mode. In dual or quad SPI mode, only the master mode of the core is supported. If other values are set, the corresponding error bit is set in SPISR and an interrupt is generated if the corresponding bit is enabled in the SPI IPIER register.

4.Loopback is allowed in standard SPI mode.