SPI Master and Slave Devices without FIFOs Performing One 8-bit/16-bit/32-bit Transfer (Optional Mode) - SPI Master and Slave Devices without FIFOs Performing One 8-bit/16-bit/32-bit Transfer (Optional Mode) - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)
Document_ID
PG153
Release_Date
2026-01-16
Version
3.2 English
Use these steps to successfully complete a SPI transaction:
  1. Start from a known state, including SPI bus arbitration.
  2. Configure the master DGIER and IPIER registers. Also configure the slave DGIER and IPIER registers as required.
  3. Write configuration data to the master SPI device SPICR register as required.
  4. Write configuration data to the slave SPI device SPICR register as required.
  5. Write the active-Low, one-hot encoded slave select address to the master SPISSR register.
  6. Write data to the slave SPI DTR as required.
  7. Write data to the master SPI DTR to start the transfer.
  8. Wait for interrupt (typically IPISR bit 4) or poll status for completion.
  9. Read the IPISR register of both master and slave SPI devices as required.
  10. Perform interrupt requests as required.
  11. Read the SPISR register of both master and slave SPI devices as required.
  12. Perform actions as required or dictated by the SPISR register data.