AXI Interface Options - 3.2 English

AXI Interface Options - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)

Document ID

PG153

Release Date

2025-01-21

Version

3.2 English

Enable XIP Mode: Enables the eXecute In Place (XIP) mode. This option also enables the AXI4 and AXI4-Lite interfaces. The choice of 24-bit or 32-bit addressing mode should be selected based on the downstream SPI device.
Figure 1. Enable XIP Mode
Enable Performance Mode: Enables the AXI4 interface. Using the AXI4 interface also enables the burst capability at the transmit and receive FIFO addresses of the core. When this option is not selected, the AXI4-Lite interface is used.