XIP Mode Debug - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

1.Make sure all the clocks and resets are connected to proper AXI interface.

2.This mode of the core supports all AXI4 transactions like FIXED, WRAP and INCR. Use a 32-bit AXI transaction for the best results. In this mode, the core operates in read-only mode.

3.Based on the number of address bits supported by the downstream device, select 24-bit or 32-bit addressing mode in the Vivado Integrated Design Environment (IDE). Based on this choice, the core considers either 24 or 32-bit from AXI4 address transactions.

4.Based on the choice of SPI mode, the core chooses the suitable SPI to read commands and add dummy cycles before accepting the correct data bits from memory.

5.The SPI transactions are observed on the SPI interface where the Slave Select line is asserted, and the SPI clock is generated by the core.

6.After the data is available in the core, the core supplies the data to an AXI4 read channel through an internal FIFO.