Hardware issues can range from link bring-up to problems seen after hours of testing. This section provides debug steps for common issues. The Vivado Design Suite debug feature is a valuable resource to use in hardware debug.
1.Use the Vivado logic analyzer for hardware debug at the SPI interface.
2.Attach the logic analyzer ports on all SPI interface ports like SS, SCK, IO0, and IO1 (also, IO2, and IO3 if used in Quad mode).
3.Generate the transactions at the AXI interface, and observe whether or not the Slave Select line is asserted, and whether or not the SPI clock is present.
4.Observe whether or not the data from the core provides sufficient setup and hold time.