Performance - 3.2 English

PG153 AXI Quad SPI Product Guide

Document ID

PG153

Release Date

2022-04-26

Version

3.2 English

For full details about performance and resource utilization, visit the Performance and Resource Utilization web page.

The performance characterization of this core was compiled using the margin system methodology. The details of the margin system characterization methodology are described in the Vivado Design Suite User Guide: Designing With IP (UG896) [Ref 2].

Note: Performance for Zynq®-7000 SoC and UltraScale™ devices is similar to 7 series devices.

The performance characterization was compiled for these families.

•Virtex®-7

•Kintex®-7

•Artix®-7

The maximum frequencies for the AXI Quad SPI core are shown in Table: AXI Quad SPI Maximum Frequencies.

Table 2-1: AXI Quad SPI Maximum Frequencies
Family	Speed Grade	AXI4-LIte Interface Fmax (MHz)	AXI4 Interface Fmax (MHz)	ext_spi_clk Fmax (MHz)
Virtex-7	-1	180	200	80
	-2	200	240	90
	-3	220	280	100
Kintex-7	-1	180	200	80
	-2	200	240	90
	-3	220	280	100
Artix-7	-1	120	150	60
	-2	140	180	70
	-3	160	200	80

Note: For xip and standard modes, ext_spi_clk may be limited to 60 MHz.

Note: UltraScale™ device frequency numbers are expected to be similar to 7 series numbers.

Note: The frequencies mentioned in the above table are specific to legacy SPI x 1 mode. They vary if we change the mode and other settings.