Clocking (SPI Clock Phase and Polarity Control) - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

Software can select any of four combinations of serial clock (SCK) phase and polarity with programmable bits in the SPICR. The clock polarity (CPOL) bit selects an active-High (clock idle state is Low) or active-Low clock (clock idle state is High). Determination of whether the edge of interest is the rising or falling edge depends on the idle state of the clock (that is, the CPOL setting).

The clock phase (CPHA) bit can be set to select one of two different transfer formats. If CPHA is 0, data is valid on the first SCK edge (rising or falling) after SS(N) has been asserted. If CPHA is 1, data is valid on the second SCK edge (rising or falling) after SS(N) has asserted.


IMPORTANT:   For successful transfers, the clock phase and polarity must be identical to those of the master SPI device and the selected slave device.

The first SCK cycle begins with a transition of the SCK signal from its idle state, which denotes the start of the data transfer. Because the clock transition from idle denotes the start of a transfer, the M68HC11 specification notes that the SS(N) line can remain active-Low between successive transfers. The specification states that this format is useful in systems with a single master and single slave. In the context of the M68HC11 specification, transmit data is placed directly in the shift register on a write to the transmit register. Consequently, it is your responsibility to ensure that the data is properly loaded into the SPISSR register prior to the first SCK edge.

The SS signal is toggled for all CPHA configurations and there is no support for SPISEL being held Low. It is required that all SS signals be routed between SPI devices internally to the FPGA. Toggling the SS signal reduces FPGA resources.