Port Descriptions - 3.2 English

Port Descriptions - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)

Document ID

PG153

Release Date

2025-01-21

Version

3.2 English

Table 1. I/O Signals
Signal Name	Interface	Signal Type	Init Status	Description
s_axi_aclk	Clock	I	-	AXI Clock. This signal in available only in legacy and XIP modes.
s_axi_aresetn	Reset	I	-	AXI Reset. This signal in available only in legacy and XIP modes.
s_axi4_aclk⁽¹⁾	Clock	I	-	AXI4 Clock. This signal in available only in enhanced and XIP modes.
s_axi4_aresetn ⁽²⁾	Reset	I	-	AXI4 Reset. This signal in available only in enhanced and XIP modes.
ext_spi_clk	Clock	I	-	This clock is used for the SPI interface. This clock should be double of the maximum SPI frequency intended at the SPI interface.
ip2intc_irpt	SPI	O	0	Interrupt control signal from SPI.
AXI Interface Signals
s_axi_*		I/O		See Appendix A of Vivado Design Suite: AXI Reference Guide (UG1037) for AXI signals. This signal is available only in legacy and XIP modes.
AXI4 Interface Signals
s_axi4_*		I/O		See Appendix A of Vivado Design Suite: AXI Reference Guide (UG1037) for AXI signals. This signal is available only in enhanced and XIP modes.
SPI Interface Signals
sck_i	SPI	I	-	SPI bus clock input. This signal is available only in Standard SPI slave mode.
sck_o	SPI	O	-	SPI bus clock output.
sck_t	SPI	O	1	3-state enable for SPI bus clock. Active-Low.
ss_i[(No. of Slaves – 1):0]	SPI	I	-	This input is not used in the design in any mode.
ss_o[(No. of Slaves – 1):0]	SPI	O	1	Output one-hot encoded, active-Low slave select vector of length n.
ss_t	SPI	O	1	3-state enable for slave select. Active-Low.
io0_i	SPI	I	-	Behaves similar to master output slave input (MOSI) input pin.
io0_o	SPI	O	-	Behaves similar to the master output slave input (MOSI) output pin. This is available only in standard SPI mode. In dual SPI mode, this signal acts as a bidirectional signal based on certain instructions.
io0_t	SPI	O	1	3-state enable master output slave input. Active-Low.
io1_i	SPI	I	-	Behaves similar to the master input slave output (MISO) input. This signal can also be considered as an `IO1_I` port in dual or quad SPI mode.
io1_o	SPI	O	-	Behaves similar to master input slave output (MISO) output. This is available only in standard SPI mode. In dual SPI mode, this signal acts as a bidirectional signal based on certain instructions.
io1_t	SPI	O	1	3-state enable master input slave output. Active-Low.
io2_i	SPI	I	-	IO2 input based on commands used. This signal is available only in quad SPI mode.
io2_o	SPI	O	-	IO2 output based on commands used. This signal is available only in quad SPI mode.
io2_t	SPI	O	1	3-state enable IO2. This signal is available only in quad SPI mode. Active-Low.
io3_i	SPI	I	-	IO3 input based on commands used. This signal is available only in quad SPI mode.
io3_o	SPI	O	-	IO3 output based on commands used. This signal is available only in quad SPI mode.
io3_t	SPI	O	1	3-state enable IO3. This signal is available only in quad SPI mode. Active-Low.
io0_1_i⁽³⁾	SPI	I	-	Behaves similar to master output slave input (MOSI) input pin.
io0_1_o⁽³⁾	SPI	O	-	Behaves similar to the master output slave input (MOSI) output pin. This signal acts as a bidirectional signal based on certain instructions.
io0__1_t⁽³⁾	SPI	O	1	3-state enable master output slave input. Active-Low.
io1_1_i⁽³⁾	SPI	I	-	Behaves similar to the master input slave output (MISO) input.
io1_1_o⁽³⁾	SPI	O	-	Behaves similar to master input slave output (MISO) output.
io1_1_t⁽³⁾	SPI	O	1	3-state enable master input slave output. Active-Low.
io2_1_i⁽³⁾	SPI	I	-	IO2 input based on commands used.
io2_1_o⁽³⁾	SPI	O	-	IO2 output based on commands used.
io2_1_t⁽³⁾	SPI	O	1	3-state enable IO2. Active-Low.
io3_1_i⁽³⁾	SPI	I	-	IO3 input based on commands used.
io3_1_o⁽³⁾	SPI	O	-	IO3 output based on commands used.
io3_1_t⁽³⁾	SPI	O	1	3-state enable IO3. Active-Low.
ss_0_i⁽³⁾	SPI	O	-	This input is not used in the design in any mode.
ss_1_i⁽³⁾	SPI	O	1	Output one-hot encoded, active-Low slave select vector of length n.
spisel	SPI	I	1	Local SPI slave select active-Low input. This is an input signal when the core is configured in standard SPI slave mode. Must be set to 1 (along with the master bit in the SPICR) in master mode.
STARTUP Interface Signals
cfgclk	STARTUP_IO	O	-	Clock is only active during configuration and during Master modes with persist set.
cfgmclk	STARTUP_IO	O	-	Free-running clock from on-chip oscillator. Nominally 50 MHz but is not characterized or specified in a data sheet.
eos	STARTUP_IO	O	-	Signal rises upon completion of the STARTUPEn sequence.
preq	STARTUP_IO	O	-	PROGRAM request to FPGA logic.
gsr	STARTUP_IO	I	-	Global set/reset.
gts	STARTUP_IO	I	-	Global 3-state input.
keyclearb	STARTUP_IO	I	-	Clear AES Decrypter Key input from battery-backed RAM (BBRAM).
usrdoneo	STARTUP_IO	I	-	User DONE pin output control.
usecclkts	STARTUP_IO	I	-	User CCLK 3-state enable input.
usedonets	STARTUP_IO	I	-	User DONE 3-state enable output.
AXI clock is expected to be faster than `ext_spi_clk`. When `ext_spi_clk` is too slow, it is advised to use FIFO depth 256. (Frequency ratio is in the range of 50 to 100.) These signals are applicable only in dual quad mode.