Feature Summary - 3.2 English

Feature Summary - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)

Document ID

PG153

Release Date

2025-01-21

Version

3.2 English

Legacy mode — AXI4-Lite interface based design
- AXI interface
  - Supports AXI4-Lite interface — legacy mode
  - All registers in the core should be accessed as 32-bit access and only through a single length AXI4-Lite transaction
- Configurable SPI modes
  - Supports standard, dual and quad SPI modes
  - Standard mode supports:
    - Master and slave SPI mode
    - MSB/LSB first transactions
    - Local loopback capability for testing
    - Multiple master and multiple slave environment
    - Optional 0 or 16 or 256 element deep (an element is a byte, a half-word or a word) transmit and receive FIFOs. Where 0 FIFO Depth refers to as no FIFO
  - Dual/quad SPI mode supports:
    - Master mode only
    - MSB first transfer only
    - SPI transfer length of 8-bits only
    - Multiple master and multiple slave environment
    - Optional 16 or 256 deep transmit and receive FIFO
    - Optional support of 6 pin SPI interface mode (In Quad mode only)
AXI4 interface mode
- AXI4 interface
  - Supports AXI4 interface
- Configurable SPI interface supports:
  - Standard, dual and quad mode of SPI configuration
  - Master mode only
  - 16 or 256 element deep transmit and receive FIFO
  - MSB-only transfer of 8-bit length at SPI flash memory
  - Multiple SPI slaves – configurable up to 32
  - Configurable XIP (execute in place) and non-XIP modes
- Enhanced mode — Non-XIP mode (burst mode access) — AXI4 design:
  - SPI read and write commands provided by master
  - Only fixed-burst transfer at DTR and DRR FIFO locations.
  - Only one read or one write transaction is acceptable at a time from AXI4 interface
  - All registers in the core should be accessed as 32-bit access and only through single length AXI4 transaction
  - WRAP transactions not supported
- Read only XIP mode — AXI4-Lite + AXI4 interface based design:
  - AXI4-Lite mode used for setting the configuration register and reading the status/debug register
  - Read commands only at SPI interface
  - INCR and WRAP read transactions at memory mapped address
  - 64 beat deep fixed internal FIFO with 32-bit data width
  - FIXED transactions unsupported

The following table defines the parameters used to configure the core.

Table 1. Core Operation Mode and Design Parameter Values
Core Operation	Parameters
Core Operation	Enable Performance Mode	Enable XIP Mode	FIFO Depth	Mode	Frequency Ratio	No. of Slaves	Slave Device	Enable STARTUPEn Primitive ⁽⁴⁾
Legacy mode			0, 16, 256	Standard	2, 4, 8, Nx16 for N = 1, 2, 3,...,128⁽¹⁾	1-32	(any)	(either)
			16, 256	Dual	2⁽²⁾	1-32	(any)	(either)
			16, 256	Quad	2⁽²⁾	1-32	(any)	(either)
Enhanced mode	x		0, 16, 256	Standard	2, 4, 8, Nx16 for N = 1, 2, 3,...,128⁽¹⁾	1-32	(any)	(either)
	x		16, 256	Dual	2⁽²⁾	1-32	(any)	(either)
	x		16, 256	Quad	2⁽²⁾	1-32	(any)	(either)
XIP mode	x	x	64	Standard	2⁽²⁾	1⁽³⁾	(any)	(either)
	x	x	64	Dual	2⁽²⁾	1⁽³⁾	(any)	(either)
	x	x	64	Quad	2⁽²⁾	1⁽³⁾	(any)	(either)
In standard mode the `ext_spi_clk` can be the same as the `axi_aclk` or `axi4_aclk` , but it should not be less than the AXI CLK or AXI4 ACLK. This mode is specifically for slow operating devices that work on the SPI protocol. Examples of these devices are EEPROMs and SPI interface-based DACs. In XIP Mode or Dual/Quad variants of Legacy/Enhanced mode, set `ext_spi_clk` to double the intended SPI clock. The Frequency Ratio parameter divides this clock by 2 to generate the SPI clock. Most of the SPI flash memory commands operate at a higher SPI clock rate with the exception of some commands which operate at a lesser frequency. It is your responsibility to configure the core with the correct `ext_spi_clk` and Frequency Ratio parameter and use the appropriate commands. If slower operating commands are executed on higher SPI clock ratios, the core does not generate an error and passes these commands to the external flash memory, but at the same time, the operation of the flash memory is not guaranteed. In XIP mode, No. of Slaves is always equal to 1 and this parameter cannot be updated. The STARTUPE2 primitive is applicable for 7 series devices. The STARTUPE3 primitive is applicable for UltraScale and later devices.