Micron Memory (Ex: N25Q256) - 3.2 English

PG153 AXI Quad SPI Product Guide

Document ID
Release Date
3.2 English

The core supports 24 and 32-bit addressing modes.

Unsupported commands/features for this memory are:

XIP mode or continuous read mode in all the memories is not supported in Legacy or enhanced mode.

All commands in dual or quad mode are supported in extended SPI mode. Dual In Out (DIO) and Quad In Out (QIO) modes are not supported. Following are the commands that are not supported by core:

°96h (Read General Purpose Read Register)

°9Bh (Interface Activation)

°E7h (Quad IO Word Read)

°E1h (4-Byte Write volatile lock bits)

Note:   No Support In Dual mode

In quad mode, the design supports the Micron memory parts with HOLD functionality only. The parts with RESET functionality are not supported in the design.

Note:   See Migrating from Micron’s N25Q to Micron’s MT25 technical note [Ref 21], for compatibility of Micron MT25Q devices with validated N25Q devices.