Common Information for Both SPI Modes - 3.2 English

PG153 AXI Quad SPI Product Guide

Document ID
Release Date
3.2 English

The core permits additional slaves to be added with automatic generation of the required decoding logic for individual slave select outputs by the master. Additional masters can also be added. However, detection of all possible conflicts is not implemented with this interface standard. To eliminate conflicts, the system software is required to arbitrate bus control.

The core can communicate with both off-chip and on-chip masters and slaves. The number of slaves is limited to 32 by the size of the slave select register. However, the number of slaves and masters affects the achievable performance in terms of frequency and resource utilization. All of the SPI core and interrupt registers are 32-bits wide. The core supports only 32-bit access to all SPI and interrupt register modules.