The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
04/26/2022 |
3.2 |
Updated Standard SPI Mode. |
|
08/06/2021 |
3.2 |
•Updated This Figure. •Added DRR NOT EMPTY feature at Byte level support. •Minor updates based on CR(s). |
|
02/04/2021 |
3.2 |
•Added AXI Read Channel Mode in User Parameters. •Updated XIP Mode and added Enable XIP Mode figure. •Updated constraints for STARTUP3. |
|
07/08/2019 |
3.2 |
Updated Table 3-3. |
|
04/04/2018 |
3.2 |
•Added constraints in dual quad mode. •Updated the supporting commands for different devices. •Updated the FIFO depth values. •Added a note mentioning one byte command mode only support. |
|
04/05/2017 |
3.2 |
•XDC updates for UltraScale+ devices. |
|
10/05/2016 |
3.2 |
•Updated the SDK directory in Note 2 n the IP Facts table. •Added a note about the AXI4-Lite write access register to the beginning of the Register Space section. •Added the Dual Quad SPI Mode to Chapter 1, Overview. •Added new I/O signals that are applicable only in dual quad mode See Table 2-2. •Added the Using the Dual Quad Mode section to Chapter 3, Designing with the Core. |
|
04/06/2016 |
3.2 |
•Added the Example Programming Sequence section to Chapter 5. •Updated the set_max_delay commands in Chapter 4. |
|
11/18/2015 |
3.2 |
Added support for UltraScale+ families. |
|
09/30/2015 |
3.2 |
•Added links to the web performance and utilization numbers. •Added information about the new STARTUPE3 primitive used with UltraScale™ devices. •Added EXT_spi_clk column to Table 2-1. •Modified the description of ss_i [(No. of Slaves – 1):0] in Table 2-4. •Added a note to the Master control register description in Table 2-7. •Added two notes to Table 4-1. •Replaced all references of Numonyx with Micron. •Removed all instances of Intel Flash (no longer makes Quad SPI flash S33 family obsolete since S3A) •Removed all instances of ST MicroElectronics as this is replaced by Micron. •Removed instances of Atmel. •Corrected Figure 3-2. |
|
11/19/2014 |
3.2 |
Added UltraScale resource numbers. |
|
10/01/2014 |
3.2 |
•Document updates only for revision change. •Removed E3 reference throughout document. •Updated Note #2 in Table 1-1: Core Operation Mode and Design Parameter Values. •Updated Table 2-2: Resource Utilization for a Kintex®-7 FPGA. •Updated STARTUP Signals in Table 2-3: I/O Signals. •Updated Bit[8] SPI Control Register. •Updated Bit[2] description in SPI Status Register. •Updated description in SPI Data Receive Register. •Updated Bit[2] description in IP Interrupt Status Register. •Removed opcode 20 in Table 3-1 and Table 3-2. •Added Table 3-3: Supported Commands in AXI Quad SPI Core in XIP Mode Commands section. •Added AXI Quad SPI Supported Devices section in Designing the Core chapter. •Added User Parameter table in Design Flow Steps chapter. •Added description for Required Constraints section. •Updated Fig. 5-1: Example Design Block Diagram. •Updated Fig. 6-1: AXI Quad SPI Example Design Test Bench. |
|
04/02/2014 |
3.2 |
•Added Spansion Flash Support (Beta Version). •Added startup interface to bring out the startup signals to be used by other IP cores. |
|
12/18/2013 |
3.1 |
Added UltraScale architecture support. |
|
10/02/2013 |
3.1 |
•Updated for the core v3.1. Version in this table aligns to core version. •Added 32-bit address support for Micron Memories in XIP mode. •Added the core design example, and test bench information. •Added information related to simulation, synthesis and implementation, and Vivado IP integrator support. •Added hardware debug and interface debug information. |
|
03/20/2013 |
1.0 |
Initial release in product guide format. This document replaces DS843. •Moved Core Mode and Parameter Value table to Chapter 1. •Revised I/O signal widths where affected. •Revised Resets section in Chapter 3. •Added 24-bit addressing restriction note to XIP mode section of Chapter 3. •Added IDE screen documentation and removed obsolete Design Parameter section in Chapter 4. |