Erase Command Sequence - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)

Document ID
PG153
Release Date
2025-01-21
Version
3.2 English
  1. Disable the master transaction by asserting the master inhibit bit of SPICR (60h), and reset the RX and TX FIFOs through SPICR.
  2. Issue sector erase command into SPIDTR to erase any specific sector followed by the flash sector address or issue the bulk erase command to erase the entire flash followed by the flash base address.

    Example: Write 0xD8 to SPIDTR

  3. Issue chip select by writing 0x00 to SPISSR.
  4. Enable master transaction by deasserting the SPICR master inhibit bit.
  5. Deassert chip select by writing 0x01 to SPISSR.
  6. Disable master transaction by asserting the SPICR master inhibit bit.