Dual/Quad Mode - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

The first write must always be a SPI command from AXI transactions, followed by the address (either 24-bit or 32-bit), then filled with the data to be transmitted. When reading the status register of the memory, then as per the command requirements, this register should be filled with dummy bytes along with a command and address (optional).

In one of these modes, the dummy bytes are required to fill in the DTR which is used for the internal count of the data reception from memory.

In commands such as dual mode read, these bytes are not transferred on the data lines, but are used by the internal logic to keep track of the number of data bytes to be read from the SPI slave memory.

If a transfer is in progress, the data in the SPI DTR is loaded into the shift register as soon as the data in the shift register is transferred to the SPI DRR and a new transfer starts. The data is held in the SPI DTR until replaced by a subsequent write. The SPI DTR is shown in This Figure and Table: SPI Data Transmit Register Description (Core Base Address + 0x68) shows the data format.

When a transmit FIFO exists, data is written directly into the FIFO and the first location in the FIFO is treated as the SPI DTR. The pointer is decremented after completion of each SPI transfer. The choice of inclusion or exclusion of the FIFO in the design is available only when the core is configured in Standard SPI mode. If the core is configured in dual or quad SPI mode, the FIFO always exists. In this mode, the FIFO depth is defined with the parameter FIFO Depth (allowed values are 16 or 256).

This register cannot be read and can only be written when it is known that space for the data is available. If an attempt to write is made on a full register or FIFO, the AXI write transaction completes with an error condition. Reading the SPI DTR is not allowed and the read transaction results in undefined data.

Figure 2-4:      SPI Data Transmit Register (Core Base Address + 0x68)

X-Ref Target - Figure 2-4

Table 2-7:      SPI Data Transmit Register Description (Core Base Address + 0x68)



Core Access

Reset Value



TX Data(1) (DN–1 – D0)

Write only


N-bit SPI transmit data. N can be 8, 16 or 32.(2)

N = 8 when the Transfer Width parameter is 8.
N = 16 when the Transfer Width parameter is 16.
N = 32 when the Transfer Width parameter is 32.


1.The DN-1 bit always represents the MSB bit irrespective of LSB first or MSB first transfer selection. When the Transfer Width parameter is 8 or 16, the unused upper bits ((AXI data width – 1) to N) are reserved.

2.In standard SPI mode, the width of this register can be 8 or 16 or 32 based on the core configuration. In dual or quad SPI mode, this register is 8-bits wide.