CPHA Equals Zero Transfer Format - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

This Figure shows the timing diagram for a standard SPI mode data write-read cycle when CPHA = 0. The waveforms are shown for CPOL = 0, LSB First = 0, and the value of generic C_SCK_RATIO = 4. All AXI and SPI signals have the same relation regarding S_AXI_AClk and SCK respectively.

Figure 3-3:      Data Write-Read Cycle on SPI Bus with CPHA = 0 and SPICR(7) = 0 for 8-bit Data

X-Ref Target - Figure 3-3


Signal SCK remains in the idle state until one-half period following the assertion of the slave select line which denotes the start of a transaction. Because assertion of the SS(N) line denotes the start of a transfer, it must be deasserted and re-asserted for sequential element transfers to the same slave device.

One bit of data is transferred per SCK clock period. Data is shifted on one edge of SCK and is sampled on the opposite edge when the data is stable. Consistent with the M68HC11 SPI specification, selection of clock polarity and a choice of two different clocking protocols on an 8/16/32-bit oriented data transfer is possible using bits in the SPICR.

The IO0 pin is equivalent to IO0 (MOSI) in standard SPI mode. The IO1 pin is equivalent to IO1 (MISO) in standard SPI mode.

The IO0 and IO1 ports behave differently depending on whether the SPI device is configured as a master or a slave. When configured as a master, the IO0 port is a serial data output port, while the IO1 is a serial data input port. The opposite is true when the device is configured as a slave; the IO1 port is a slave serial data output port and the IO0 is a serial data input port. There can be only one master and one slave transmitting data at any given time. The bus architecture provides limited contention error detection (that is, multiple devices driving the shared IO1 and IO0 signals) and requires the software to provide arbitration to prevent possible contention errors.

All SCK, IO0, and IO1 pins of all devices are hard-wired together. For all transactions, a single SPI device is configured as a master and all other SPI devices on the SPI bus are configured as slaves.

The single master drives the SCK and IO0 pins to the SCK and IO0 pins of the slaves. The uniquely-selected slave device drives data from its IO1 pin to the IO1 master pin, thus realizing full-duplex communication.

The Nth bit of the SS(N) signal selects the Nth SPI slave with an active-Low signal. All other slave devices ignore both SCK and IO0 signals. In addition, the non-selected slaves (that is, SS pin High) drive their IO1 pin to 3-state so as not to interfere with SPI bus activities. When external slave SPI devices are implemented, the SCK, IO0 and IO1, as well as the needed SS(N) signals, are brought out to pins. All signals are true 3-state bus signals and erroneous external bus activity can corrupt internal transfers when both internal and external devices are present.

Ensure that the external pull-up or pull-down of external SPI 3-state signals are consistent with the sink/source capability of the FPGA I/O drivers. The I/O drivers can be configured for different drive strengths, as well as internal pull-ups. The 3-state signals for multiple external slaves can be implemented per the system design requirements, but the external bus must follow the SPI M68HC11 specifications.