Transfer End Period - 3.2 English

PG153 AXI Quad SPI Product Guide

Document ID
Release Date
3.2 English

The definition of the transfer end period for the AXI Quad SPI core is consistent with the M68HC11 reference manual. The SPI transfer is signaled complete when the SPIF flag is set. However, depending on the configuration of the SPI system, there might be additional tasks to be performed before the system can consider the transfer complete.

When configured without FIFOs, the Rx_Full bit (1) in the SPISR is set to denote the end of a transfer. When data is available in the SPI DRR register, bit 4 of the IPISR is asserted as well. The data in the SPI DRR is sampled on the same clock edge as the assertion of the SPI DRR register full interrupt.

When the SPI device is configured as a master without FIFOs, these steps occur:

Rx_Empty bit (0), Tx_Full bit, and bit 3 in the SPISR are cleared.

Tx_Empty bit (2), Rx_Full bit, and bit 1 in SPISR are set.

DRR Full bit (4), Slave MODF bit, and bit 1 in the IPISR are set on the first rising AXI clock edge after the end of the last SCK cycle.

Note:   The end of the last SCK cycle is a transition on SCK for CPHA = 0, but is not denoted by a transition on SCK for CPHA = 1 (see This Figure and This Figure). However, the internal master clock provides this SCK edge which prompts the setting and clearing of the bits noted.

In this design, a counter is implemented that permits the simultaneous setting of SPISR and IPISR bits for both master and slave SPI devices. External SPI slave devices can use an internal AXI clock that is asynchronous to the SCK clock. This can cause status bits in the SPISR and IPISR to be inconsistent with each other. Therefore, the AXI Quad SPI core cannot be used in a system with external SPI slave devices that do not use the AXI clock.

When the AXI Quad SPI core is configured with FIFOs and a series of consecutive SPI 8-bit/16-bit/32-bit element transfers are performed (based on parameter settings), the SPISR bits and IPISR do indicate completion of the first and the last SPI transfers with no indication of intermediate transfers. The only way to monitor when intermediate transfers are completed is to monitor the receive FIFO occupancy number. There is also an interrupt when the transmit FIFO is half empty, bit 6 of IPISR.

When the SPI device is configured as a slave, the setting/clearing of the bits discussed previously for a master coincides with the setting or clearing of the master bits for both cases of CPHA = 0 and CPHA = 1. Keep in mind that for CPHA = 1 (that is, no SCK edge denoting the end of the last clock period), the slave has no way of knowing when the end of the last SCK period occurs, unless an AXI clock period counter was included in the SPI slave device.