The Device Global Interrupt Enable Register (DGIER) is used to globally enable the final interrupt output from the interrupt controller as shown in This Figure and described in Table: Device Global Interrupt Enable Register Description (Core Base Address + 0x1C). This is a read/write bit and is cleared on reset.
Figure 2-9: Device Global Interrupt Enable Register (Core Base Address + 0x1C)
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X-Ref Target - Figure 2-9
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Table 2-12: Device Global Interrupt Enable Register Description (Core Base Address + 0x1C)
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Bits
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Name
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Core Access
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Reset Value
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Description
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31
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GIE
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R/W
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0
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Global Interrupt Enable.
Allows passing all individually enabled interrupts to the interrupt controller.
When set to:
0 = Disabled.
1 = Enabled.
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30:0
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Reserved
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N/A
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N/A
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Reserved
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