Upgrading in the Vivado Design Suite - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)

Document ID
PG153
Release Date
2025-01-21
Version
3.2 English

The SPISEL port is hidden when master SPI mode is selected. This port is internally driven to VCC in master mode. In case of slave SPI operation mode, this port is available and should be connected to the Slave Select port of other SPI masters.

There were several I/O ports added that are applicable only in dual quad mode. See Table 1.