Unsupported Features - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)

Document ID
PG153
Release Date
2025-01-21
Version
3.2 English

These features relate to the AXI4 interface and are not supported by the core.

  • INCR of length more than 1 and WRAP bursts in enhanced mode
  • FIXED burst in XIP mode
  • Narrow bursts in enhanced mode (only the last 8-bits from the 32 burst bits are valid in enhanced mode)
  • Write channel and transactions in XIP mode
  • Atomic, locked and cache transactions
  • Debug/secure and user signals
  • Out-of-order transactions
  • Region signals
  • Quality of Service (QOS) signals
  • Holes in byte strobes
  • Barrier transactions
  • Write interleaving
  • User signals
  • AXI TrustZone and low-power state
  • Simultaneous read and write transactions in enhanced mode
  • Un-aligned address when the core is configured in read-only XIP mode
  • Byte access in XIP mode
  • Standard Slave mode when the serial clock (SCK) ratio is 2 is not supported by the core.
  • In enhance mode, IP waits for s_axi4_rready to generate the first s_axi4_rvalid.