SPI Status Register - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)
Document ID
PG153
Release Date
2025-01-21
Version
3.2 English

The SPI Status Register (SPISR) is a read-only register that provides the status of some aspects of the AXI Quad SPI core to the programmer. The bit assignment in the SPISR is shown in the following figure and described in the following table. Writing to the SPISR does not modify the register contents.

Figure 1. SPI Status Register (Core Base Address + 0x64)
Table 1. SPI Status Register Description (Core Base Address + 0x64)
Bits Name Core Access Reset Value Description
31:11 Reserved N/A N/A Reserved
10 Command Error Read 0

Command error flag.

When set to:

  • 0 = Default.
  • 1 = When the core is configured in dual/quad SPI mode and the first entry in the SPI DTR FIFO (after reset) do not match with the supported command list for the particular memory, this bit is set.
Note: Command error is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface.
9 Loopback Error Read 0

Loopback error flag.

When set to:

  • 0= Default. The loopback bit in the control register is at default state.
  • 1 = When the SPI command, address, and data bits are set to be transferred in other than standard SPI protocol mode and this bit is set in control register (SPICR).
Note: Loopback is only allowed when the core is configured in standard mode. Other modes setting of the bit causes an error and the interrupt bit is set in legacy or enhanced mode AXI4 interface.
8 MSB Error Read 0

MSB error flag.

When set to:

  • 0= Default.
  • 1 = This bit is set when the core is configured to transfer the SPI transactions in either dual or quad SPI mode and LSB first bit is set in the control register (SPICR).
Note: In dual/quad SPI mode, only the MSB first mode of the core is allowed. MSB error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface.
7 Slave Mode Error Read 1

Slave mode error flag.

When set to:

  • 1 = This bit is set when the core is configured with dual or quad SPI mode and the master is set to 0 in the control register (SPICR).
  • 0 = Master mode is set in the control register (SPICR).
Note: Quad SPI mode, only the master mode of the core is allowed. Slave mode error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced AXI4 mode interface.
6

CPOL_CPHA_

Error

 Read 0

CPOL_CPHA_Error flag.

When set to:

  • 0 = Default.

  • 1 = The CPOL and CPHA are set to 01 or 10.

    When the SPI memory is chosen as either Winbond, Micron or Spansion or Macronix and CPOL and CPHA are configured as 01 or 10, this bit is set.

Note: These memories support CPOL=CPHA mode in 00 or in 11 mode. CPOL_CPHA_Error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface.
5

Slave_Mode_

Select

 Read 1

Slave_Mode_Select flag.

This flag is asserted when the core is configured in slave mode. Slave_Mode_Select is activated as soon as the master SPI core asserts the chip select pin for the core.

  • 1 = Default in standard mode.
  • 0 = Asserted when core configured in slave mode and selected by external SPI master.
4 MODF Read 0

Mode-fault error flag.

This flag is set if the SS signal goes active while the SPI device is configured as a master. MODF is automatically cleared by reading the SPISR. A Low-to-High MODF transition generates a single-cycle strobe interrupt.

0 = No error.

1 = Error condition detected.
3 Tx_Full Read 0

Transmit full.

When a transmit FIFO exists, this bit is set High when the transmit FIFO is full.

Note: When FIFOs do not exist, this bit is set High when an AXI write to the transmit register has been made (this option is available only in standard SPI mode). This bit is cleared when the SPI transfer is completed.
2 Tx_Empty Read 1

Transmit empty.

When a transmit FIFO exists, this bit is set to High when the transmit FIFO is empty. This bit goes High as soon as the TX FIFO becomes empty. While this bit is High, the last byte of the data that is to be transmitted would still be in the pipeline. The occupancy of the FIFO is decremented with the completion of each SPI transfer.

Note: When FIFOs do not exist, this bit is set with the completion of an SPI transfer (this option is available only in standard SPI mode). Either with or without FIFOs, this bit is cleared on an AXI write to the FIFO or transmit register. For Dual/Quad SPI mode, the FIFO is always present in the core.
1 Rx_Full Read 0

Receive full.

When a receive FIFO exists, this bit is set High when the receive FIFO is full. The occupancy of the FIFO is incremented with the completion of each SPI transaction.

Note: When FIFOs do not exist, this bit is set High when an SPI transfer has completed (this option is available only in standard SPI mode). Rx_Empty and Rx_Full are complements in this case.
0 Rx_Empty Read 1

Receive Empty.

When a receive FIFO exists, this bit is set High when the receive FIFO is empty. The occupancy of the FIFO is decremented with each FIFO read operation.

Note: When FIFOs do not exist, this bit is set High when the receive register has been read (this option is available only in standard SPI mode). This bit is cleared at the end of a successful SPI transfer. For dual/quad SPI mode, the FIFO is always present in the core.