Micron Memory - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)

Document ID
PG153
Release Date
2025-01-21
Version
3.2 English

In Micron memory, the volatile as well as nonvolatile configuration registers are left with the default configuration of dummy cycles. That is, VCR[7:4] and NVCR[15:12] are set to 1111. The core behavior is based on this assumption only and if these dummy cycle register values are changed, the core behavior is not guaranteed.

At the start of each new transaction, the core sends the respective command, address and required dummy cycles and then receives data.