Enable STARTUPE2 Primitive Parameter - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

STARTUPE2 is a primitive in the Xilinx device. This primitive can be used after the FPGA configuration in the design. For more understanding on the use of this primitive, read the targeted FPGA user guide. This primitive can be included in the design by selecting the Enable STARTUPE2 Primitive parameter. The STARTUPE2 primitive is present in 7 series and Zynq®-7000 SoC devices, This primitive has a dedicated clock pin that can be used to provide the SPI clock to the slave memory. The output ports of the STARTUP primitive are taken to the top interface of the core as the STARTUPE2 interface. Spartan-7 7S6 and 7S15 FPGAs do not support the STARTUPE2.CLK - UserClk startup clock pin.

For more information, refer to the 7-Series FPGAs Configuration User Guide (UG470)[Ref 17].