Enhanced Mode - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

In this mode, the AXI4-Lite interface for the core is replaced with the AXI4 interface. This mode also supports standard, dual and quad modes depending on the Mode option setting. The target slave memory can be chosen by setting the Slave Device option to Mixed, Winbond, Micron, Macronix, or Spansion. All of the registers are mapped to the same offset as with the AXI4-Lite interface. The AXI4 interface is allowed to do burst transactions at the data transmit register and data receive register only. All other registers should be single access only. This should be noted while designing the application for the core.

The DTR and DRR FIFOs are configurable to 16 or 256 beat depth. The core supports the same functionality as the AXI4-Lite interface. The added advantage for this mode is burst capability at the DTR and DRR locations, reducing the overhead of reading and writing data to and from the core at the AXI4 interface side.