When enabled by the parameter Enable FIFO, the transmit FIFO and receive FIFO are implemented on both the transmit and receive paths. The width of the transmit FIFO and receive FIFO are the same and depend on the Transaction Width parameter. The FIFOs can be enabled or disabled with depth variable at 16 or 256 when enabled in Standard SPI mode. In dual and quad SPI modes, the FIFO depth is 16 or 256 locations (bytes).