Dual/Quad SPI Mode Transactions - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

In this mode, the core must be configured in master mode only. Otherwise, an error interrupt is generated.

The sequence flow to operate the core in dual mode from the core point of view is shown. Check the inter-dependency of the commands before filling the SPI DTR register and enabling the SPI core to start the transaction.

1.Ensure that Mode is Dual and that Slave Device is set for the correct SPI slave memory.

2.Ensure that the instructions driven by the required SPI clock and set by Frequency Ratio, are listed.

3.Set the FIFO Depth parameter. This parameter can either be 16 or 256.

4.Write to the soft reset register to reset the core. This reset is active for 16 AXI cycles, during which each FIFO register is in the reset state.

5.Write to the SPICR register to put the core in master mode; set the CPOL, CPHA values, and make sure that the master transaction inhibit bit is set.

6.Write to the IPIER and IPISR registers to enable the required interrupts.

7.Write to the SPI DTR with the command, address, dummy, and data bytes to be transmitted in the same sequence provided in the data sheet of the target device.

8.Write to the SPI DTR with the number of data bytes intended to be read or written to memory along with command, address, and dummy bytes.

9.Write to the SPISSR register to assert the chip select signal from the core.

10.Write to the SPICR register to enable the master transaction inhibit bit, so that the core starts the SPI clock.

11.For a write, wait until the DTR empty interrupt is generated.

12.When the DTR empty interrupt is generated, data can still be written into the SPI DTR for further transactions if the slave select register remains unchanged (such as if the slave is selected).

13.If further data is written, the SPISSR register continues to be asserted; only the SPI clock is stopped. When the DTR FIFO is not empty, the SPI clock is enabled again and data is transmitted.

14.When reading, step 11, step 12, and step 13 also apply. Fill the DTR FIFO with any random data beats while reading the SPI slave memory.

15.Disabling the selected slave by setting all SPISSR register bits to 1 (or carrying out the master transactions inhibit bit set to 1 in the SPICR register), the SPI clock is stopped.

16.After disabling the selected slave by setting all SPISSR register bits to 1, If the SPI DTR FIFO is filled again, the core considers this a fresh transaction and compares the first entry in the DTR FIFO with the supported commands.

17.Between new transactions, make sure that the SPI DTR and DRR FIFOs are reset by writing into the SPICR register bits while the slave is deselected. This allows these two FIFOs to be reset and the first entry of the DTR FIFO to be compared with the supported commands.

Note:   Core will support both the approaches of writing all at a time to the DTR (After Master inhibit set, Write all (Command,Address, Data) to the DTR then, Resetting the Master inhibit as mentioned in (step 7)) and writing one at a time to the DTR (After Master inhibit set, Write command to the SPI DTR , and then reset the inhibit, and similarly repeat the above procedure for Address,Data).