AXI4-Lite Interface - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)

Document ID
PG153
Release Date
2025-01-21
Version
3.2 English

If the AXI4-Lite interface is chosen, all the registers including the SPI DTR and SPI DRR are 32-bit, single-access registers. The SPI DTR and SPI DRR registers have only 8 valid bits out of 32.