AXI4-Lite Interface Hardware Error Detection - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

The SPI architecture relies on software-controlled bus arbitration for multi-master configurations to avoid conflicts and errors. However, limited error detection is implemented in the SPI hardware. The first error detection mechanism to be discussed is contention error detection. This mechanism detects when a SPI device, configured as a master, is selected (that is, its SS bit is asserted) by another SPI device which is simultaneously configured as master. In this scenario, the master being selected as a slave immediately drives its outputs as necessary to avoid hardware damage due to simultaneous drive contention. The master also sets the mode-fault error (MODF) bit in the SPISR. This bit is automatically cleared by reading the SPISR. Following a MODF error, the master must be disabled and re-enabled with correct data. When configured with FIFOs, the process might require clearing the FIFOs.

A similar error detection mechanism has been implemented for SPI slave devices. The detected error occurs when a SPI device configured as a slave, but not enabled, is selected (that is, its SS bit is asserted) by another SPI device. When this condition is detected, IPISR bit 1 is set by a strobe to the IPISR register.

Underrun and overrun condition error detection is also provided. Underrun conditions can happen only when operated in slave mode. This condition occurs when a master commands a transfer, but the slave does not have data in the transmit register or FIFO to transfer. In this case, the slave underrun interrupt is asserted and the slave shift register is loaded with all zeros for transmission. An overrun condition can occur to both master and slave devices where a transfer occurs when the receive register or FIFO is full. During an overrun condition, the data received in that transfer is not registered (it is lost) and the IPISR overrun interrupt bit 5 is asserted.