The SPI Receive FIFO Occupancy Register (RX_FIFO_OCY) is present only if the AXI Quad SPI core is configured with FIFOs (FIFO Depth = 16 or 256). If the register is present and if the receive FIFO is not empty, the register contains a four-bit, right-justified value that is one less than the number of elements in the FIFO (occupancy minus one).
This register is read-only. A write to it (or of a read when the FIFO is empty) does not affect the register contents. The only reliable way to determine that the receive FIFO is empty/full is by reading the Rx_Empty/Rx_Full status bit in the SPI status register.
The receive FIFO occupancy register is shown in the following figure, while the specifics of the data format are described in the following table.
Bits | Name | Core Access | Reset Value (hex) | Description |
---|---|---|---|---|
31–log(FIFO Depth) | Reserved | N/A | N/A | Reserved |
(log(FIFO Depth)–1):0 | Occupancy Value | Read | 0 | The binary value plus 1 yields the occupancy. |