AXI4-Lite Interface Dual/Quad SPI Mode — Optional FIFO Depth - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)

Document ID
PG153
Release Date
2025-01-21
Version
3.2 English

When the core is configured in dual or quad SPI mode, the FIFO is always present and there is the option to choose its depth. The depth of this FIFO can be either 16 or 256. The width of the FIFO in this mode is always 8 bits.