Interrupt Register Set Description - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

The AXI Quad SPI core has many distinct interrupts that are sent to the interrupt controller. The core interrupt controller allows each interrupt to be enabled independently (using the IP interrupt enable register (IPIER)). The interrupt registers are contained within the interrupt controller. An interrupt strobe can be generated under multiple conditions or only after a transfer completion. In standard, dual or quad SPI mode, and master mode, when the parameter FIFO Depth is set to 16 or 256, almost all of the interrupts shown in Table: IP Interrupt Status Register Description (Core Base Address + 0x20) are available.

In Standard SPI mode, when FIFO Depth is set to 0, all of the interrupts are available except:

Bit[6]: Transmit FIFO half empty

Bit[8]: DRR not empty (not present in this mode)