The SPI Slave Select Register (SPISSR) contains an active-Low, one-hot encoded slave select vector SS of length N, where N is the number of slaves set by the No. of Slaves parameter. The SS vector occupies the right-most bits of the register. At most, one bit can be asserted Low. This bit denotes the slave with which the local master communicates. The bit assignment in the SPISSR is shown in This Figure and described in Table: SPI Slave Select Register Description (Core Base Address + 0x70).
Figure 2-6: SPI Slave Select Register (Core Base Address + 0x70)
|
X-Ref Target - Figure 2-6
|
Table 2-9: SPI Slave Select Register Description (Core Base Address + 0x70)
|
Bits
|
Name
|
Core Access
|
Reset Value
|
Description
|
|
31:N
|
Reserved
|
N/A
|
N/A
|
Reserved
|
|
[N–1]:0
|
Selected Slave
|
R/W
|
1
|
Active-Low, one-hot encoded slave select vector of length N-bits. N must be £ the data bus width (32-bit).
The slaves are numbered right to left starting at zero with the LSB. The slave numbers correspond to the indexes of signal SS.
|
