SPI Master and Slave Devices with FIFOs Where Some Initial Data is Written to FIFOs, the SPI Transfer is Started, Data is Written to the FIFOs as Fast or Faster than the SPI Transfer and Multiple Discrete 8-bit Transfers are Performed (Optional Mode). - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)
Document ID
PG153
Release Date
2025-01-21
Version
3.2 English
Use these steps to successfully complete a SPI transaction:
  1. Start from the proper state including SPI bus arbitration.
  2. Configure the master DGIER and IPIER registers. Also configure the slave DGIER and IPIER registers as required.
  3. Write configuration data to the master SPI device SPICR register as required.
  4. Write configuration data to the slave SPI device SPICR register as required.
  5. Write the active-Low, one-hot encoded slave select address to the master SPISSR register.
  6. Write initial data to the slave transmit FIFO as required.
  7. Write initial data to the master transmit FIFO.
  8. Write the enable bit to the master SPICR register which starts the transfer.
  9. Continue writing data to both the master and slave FIFOs.
  10. Wait for interrupt (typically IPISR bit 4) or poll status for completion.
  11. Read the IPISR register of both master and slave SPI devices as required.
  12. Perform interrupt requests as required.
  13. Read the SPISR register of both master and slave SPI devices as required.
  14. Perform actions as required or dictated by SPISR register data.