- Configurable AXI4 interface; when
configured with an AXI4-Lite interface the core is backward compatible with
version 1.00 of the core (legacy mode)
- Configurable AXI4 interface for burst mode
operation for the Data Receive Register (DRR) and the Data Transmit Register (DTR) FIFO
-
Configurable eXecute In Place (XIP) mode of
operation
- Connects as a 32-bit slave on either AXI4-Lite or AXI4 interface
- Configurable SPI modes:
- Standard SPI mode
- Dual SPI mode
- Quad SPI mode
-
Programmable SPI clock phase and
polarity
-
Configurable FIFO depth (16 or 256 element deep
in Dual/Quad/Standard SPI mode) and fixed FIFO depth of 16 in XIP
mode
- Configurable Slave Memories in
dual and quad modes are: Mixed, Micron, Winbond, Macronix, and
Spansion (Beta Version)