Features - 3.2 English

PG153 AXI Quad SPI Product Guide

Document ID

PG153

Release Date

2022-04-26

Version

3.2 English

•Configurable AXI4 interface; when configured with an AXI4-Lite interface the core is backward compatible with version 1.00 of the core (legacy mode)

•Configurable AXI4 interface for burst mode operation for the Data Receive Register (DRR) and the Data Transmit Register (DTR) FIFO

•Configurable eXecute In Place (XIP) mode of operation

•Connects as a 32-bit slave on either AXI4-Lite or AXI4 interface

•Configurable SPI modes:

°Standard SPI mode

°Dual SPI mode

°Quad SPI mode

•Programmable SPI clock phase and polarity

•Configurable FIFO depth (16 or 256 element deep in Dual/Quad/Standard SPI mode) and fixed FIFO depth of 16 in XIP mode

•Configurable Slave Memories in dual and quad modes are: Mixed, Micron, Winbond, Macronix, and Spansion (Beta Version)

LogiCORE IP Facts Table
Core Specifics
Supported Device Family⁽¹⁾	UltraScale+™ UltraScale™ Zynq®-7000 SoC 7 Series FPGAs
Supported User Interfaces	AXI4, AXI4-Lite
Resources	Performance and Resource Utilization web page
Provided with Core
Design Files	VHDL
Example Design	VHDL
Test Bench	VHDL
Constraints File	Xilinx Design Constraints (XDC)
Simulation Model	Not Provided
Supported S/W Driver⁽²⁾	Standalone and Linux
Tested Design Flows⁽³⁾
Design Entry	Vivado® Design Suite
Simulation	For a list of supported simulators, see the Xilinx Design Tools: Release Notes Guide
Synthesis	Vivado synthesis
Support
Release Notes and Known Issues	Master Answer Record: 54408
All Vivado IP Change Logs	Master Vivado IP Change Logs: 72775
Xilinx Support Web page
Notes: 1.For a complete list of supported devices, see the Vivado IP catalog. 2.Standalone driver details can be found in the Vitis directory (<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm) on the Xilinx Wiki page. 3.For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.