For comprehensive information about Vivado Design Suite simulation components, as well as information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 7].
For information about simulating the example design, see Simulating the Example Design.
IMPORTANT: For cores targeting 7 series FPGAs or Zynq-7000 devices, UNIFAST libraries are not supported. Xilinx IP is tested and qualified with UNISIM libraries only.