XIP Mode Commands - 3.2 English - PG153

AXI Quad SPI LogiCORE IP Product Guide (PG153)
Document ID
PG153
Release Date
2025-01-21
Version
3.2 English

In XIP mode, the core supports three read commands:

  • Standard mode: fast read – 0x0Bh
  • Dual mode: fast read dual I/O – 0xBBh
  • Quad mode: fast read quad I/O – 0xEBh
Table 1. Supported Commands in AXI Quad SPI Core

Command Opcode

Command Description

 Winbond Spansion Numonyx/Micron Macronix
9E/9F JEDEC ID (electronic identity of each flash memory)/SPAN_RDID in SPANSION / READ ID in Numonyx in Macronix Yes Yes Yes Yes
0B Fast read(read operating at highest possible frequency of flash) Yes Yes Yes Yes
3B Fast read dual output(2 lines fast read) Yes Yes Yes Yes
BB Fast read dual I/O(similar to (3Bh) ,but with the capability to input the Address bits (A23-0) two bits per clock) Yes Yes Yes Yes
6B Fast read quad output(fast read 4 lines) Yes Yes Yes Yes
EB Fast read quad I/O(similar to (3Bh) ,but with the capability to input the Address bits (A23-0) 4 bits per clock.,) Yes Yes Yes Yes
06 WEN(write enable sets the Write Enable Latch (WEL) bit in the Status Register to a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register instruction.) WRITE ENABLE in Numonyx / in Macronix Yes Yes Yes Yes
04 Write disable(sets WEL to 0) Yes Yes Yes Yes
02 Page program(The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations) Yes Yes Yes Yes
32 Quad page program(page program with 4 pins) Yes Yes Yes No
D8 Block erase(The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh) / SECTOR ERASE in Numonyx Yes Yes Yes Yes
01 Write status register(Only Non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7, 5, 4, 3, 2 of Status Register-1) and QE, SRP1(bits 9 and 8 of Status Register-2) can be written to.) Yes Yes Yes Yes
03 Read data(The Read Data instruction allows one more data bytes to be sequentially read from the memory.) Yes Yes Yes Yes
05 Read SR-1(The Read Status Register instructions allow the 8-bit Status Registers to be read.) Yes Yes Yes Yes
7A Erase resume,(The Erase Resume instruction "7Ah" must be written to resume the Sector or Block Erase operation after an Erase Suspend.) Yes Yes Yes No
75 Erase suspend,(The Erase Suspend instruction "75h", allows the system to interrupt a Sector or Block Erase operation and then read from or program data to, any other sectors or blocks.) Yes Yes Yes No
C7 Chip erase, (The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh) (C4 in case of numonyx) Yes Yes Yes Yes
4B Read unique ID.(The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each flash device.) OTP Read for spansion and Numonyx Yes Yes Yes No
13 Read (4 byte address)-(The instruction code for the ReadData Bytes using 4 Bytes Address (READ4BYTE) instruction is followed by a 4-byte address (A31-A0), each bit being latched-in during the rising edge of Serial Clock (C). ) No Yes Yes Yes
0C Read fast(4 byte address) No Yes Yes Yes
5A

5A--->Read serial flash discoverable parameters(allows reading the SerialFlash Discovery Parameter area (SFDP), composed of 2048 read-only bytes containing operating characteristics and vendor specific information. The SFDP area is factory programmed./READ SERIAL FLASH DISCOVERY

PARAMETER in Numonyx

 No Yes Yes Yes
3C Fast Read Dual out(4-byte address) No Yes Yes Yes
BC Dual I/O read(4 byte address) No Yes Yes Yes
6C Read quad out(4 byte address) No Yes Yes Yes
EC Quad I/O read(4 byte address),High freq,4 lines, addr on 2 lines No Yes Yes Yes
12 Page program (4 byte address),Page program with 4byte addressing. No Yes Yes Yes
42 Program OTP .The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from 1 to 0, only).These 64 bytes can be permanently locked by a particular Program OTP (POTP) sequence. No Yes Yes Yes
E8

Read lock register.(There are two software protected modes, SPM1 and SPM2, that can be combined to protectthe memory array as required. The SPM2 can be locked by hardware with the help of the input pin.

SPMThe first software protected mode (SPM1) is managed by specific Lock Registers assigned to each 64 Kbyte sector./READ VOLATILE LOCK BITS in Numonyx

 No Yes Yes Yes
85 Read volatile config register. (The Non Volatile Configuration Register (NVCR) bits affects the default memory configuration after power-on. It can be used to make the memory start in the configuration to fit the application requirements. Program Suspend in spansion No Yes Yes Yes
E9 Exit 4 byte address mode. (The Exit 4-byte address mode (EX4BYTEADDR) instruction disables 4-byte address mode.) Command is password unlock in spansion No Yes Yes Yes
52 Block Erase /32KB SUBSECTOR ERASE in Numonyx Yes No Yes Yes
A2 Dual input fast program. Highest freq, The dual input fast program (DIFP) instruction makes it possible to program up to 256 bytesusing two input pins at the same time (by changing bits from '1' to '0') No No Yes No
D2 Dual input extended fast program. The Dual Input Extended Fast Program (DIEFP) instruction is an enhanced version of the Dual Input Fast Program instruction, allowing to transmit address across two data lines. No No Yes No
E5 Write to lock register/Write Volatile Lock Bits in Numonyx No No Yes No
70 Read flag status register No No Yes No
50 Clear flag status register No No Yes No
B5 Read NV config register No No Yes No
B1 Write NV config register /Enter Secured OTP in Macronix No No Yes Yes
81 Write volatile config register No No Yes No
65 Read volatile enhanced config register No No Yes No
61 Write volatile enhanced config register. The Volatile Enhanced Configuration Register (VECR) affects the memory configuration after every execution of Write Volatile Enhanced Configuration Register (WRVECR) instruction. This instruction overwrites the memory configuration set during the POR sequence by the Non Volatile Configuration Register (NVCR). Its purpose is enabling of QIO-SPI protocol and DIO-SPI protocol. No No Yes No
B7 Enter 4 byte address mode No No Yes Yes
C5 Write extended addr reg. No No Yes Yes
C8 Read extended addr register No No Yes Yes
66 Reset enable No No Yes Yes
99

Reset memory. The Reset Enable and Reset Memory operation is used as a system software reset that puts the device in the power-on reset condition.

 No No Yes Yes
20 Subsector erase. The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must have been executed previously/SECTOR ERASE in Macronix Yes No Yes Yes
35 Read SR-2/ ENTER Quad IO Mode in Numonyx Yes Yes Yes Yes
B9 Power down. Although the standby current during Normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications. Bank Register Access in spansion enter deep power down in Numonyx in Macronix Yes Yes Yes Yes
A3 HPM. The High Performance Mode (HPM) instruction must be executed prior to Dual or Quad I/O instructions when operating at high frequencies (see FR and FR1 in AC Electrical Characteristics). This instruction allows pre-charging of internal charge pumps so the voltages required for accessing the Flash memory array are readily available. Yes No No No
FF Continuous read mode reset. For Fast Read Dual/Quad I/O operations, "Continuous Read Mode" Bits (M7-0) are implemented to further reduce instruction overhead. Mode Bit Reset in spansion No Yes No No
AB Release Power down/HPM. The Release from Power-down or High performance Mode/Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state or High Performance Mode, or obtain the devices electronic identification (ID) number. Command is Read Electronic Signature in spansion release from deep power down in Numonyx in Macronix Read Electronic Id Yes Yes Yes Yes
90 Device ID. The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. Yes Yes No Yes
30 Clear SR-1/PGM/ERS Resume in Macronix No Yes No Yes
15 Autoboot reg write/Read config register in Macronix No No No Yes
16 Bank register read. Bank address register may need to be changed during a suspend to reach a sector for read or program. / Read Fast Boot Register in Macronix No Yes No Yes
17 Bank register write / Write Fast Boot Register in Macronix No Yes No Yes
38

EXTENDED QUAD INPUT FAST PROGRAM(enhanced version of the Quad Input Fast Program instruction, allowing parallel input on the 4 input pins, including the address being sent to the device.)

 No Yes Yes Yes
34 Quad page program ( 4 byte address) No Yes Yes No
60 Bulk erase/CHIP ERASE in Macronix Yes Yes No Yes
E0 DYBRD. It may be necessary to remove and restore dynamic protection during erase suspend to allow programming during erase suspend / 4-BYTE READ VOLATILE LOCK in Numonyx/ Write DPB Register in Macronix BITS No Yes Yes Yes
E1 DYBWR / 4-BYTE WRITE VOLATILE LOCK BITS in Numonyx / Write DPB Register in Macronix No Yes Yes Yes
E2 PPBRD. Allowed for checking persistent protection before attempting a program command during erase suspend. / READ NonVolatile Lock BITS in Numonyx / Read SPB Status in Macronix No Yes Yes Yes
E3

PPB program octal word read quad I/O (for windbond). The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four address bits (A0, A1, A2, A3) must equal 0. As a result, the four dummy clocks are not required, which further reduces the instruction overhead allowing even faster random access for code execution (XIP). / Write NonVolatile Lock Bits in Numonyx

 Yes Yes Yes Yes
E4 PPB erase / Erase NonVolatile Lock Bits in Numonyx No Yes Yes Yes
2B ASP Read /READ Security Register in Macronix No Yes No Yes
2F ASP program/WRITE Security Register in Macronix No Yes No Yes
A7 PPB lock bit read / READ GLOBAL FREEZE BIT in Numonyx No Yes Yes No
A6 PPB lock bit write /WRITE GLOBAL FREEZE BIT in Numonyx No Yes Yes No
E7 Quad IO word read /Password Read in Spansion No Yes No No
F0 Reset No Yes No No
8A Program resume No Yes No No
07 Read SR-2 SP No Yes No No
DC Erase 256KB (4 byte addr)/4-BYTE SECTOR ERASE in Numonyx No Yes Yes Yes
27 Read 4 byte password No No Yes Yes
28 Write password No No Yes Yes
29 Unlock password No No Yes Yes
3E 4xIO page program/ 4-BYTE QUAD INPUT EXTENDED FAST PROGRAM in Numonyx No No Yes Yes
21 Sector erase 4 byte address/ 4-BYTE 4KB SUBSECTOR ERASE in Numonyx No No Yes Yes
5C Block erase 32kb/4-BYTE 32KB SUBSECTOR ERASE in Numonyx No No Yes Yes
C0 Set burst read length No No No Yes
18 Erase fast boot register No No No Yes
F5 Reset qpi mode / Reset Quad IO Mode in Numonyx No No Yes Yes
2D Read lock register/Read Sector Protection in Numonyx No No Yes Yes
2C Write lock register/ PROGRAM SECTOR PROTECTION in Numonyx No No Yes Yes
AF QPI ID/MULTIPLE I/O READ ID in Numonyx No No Yes Yes
B0 PGM/ERS Suspend (suspends Program/Erase) No No No Yes
C4 DIE ERASE No No Yes No
68 Write Protection Selection WPSEL No No No Yes
C1 Exit secured OTP No No No Yes
7E Gang Block Lock No No No Yes
98 Gang Block UnLock No No No Yes
00 NOP No No No Yes

Following are the unsupported Commands for Dual/Quad SPI Mode across different memories of Winbond, Micron, Spansion, and Macronix.