Enhanced Mode Debug - 3.2 English - PG153

1. Make sure the clock is connected to the s_axi4_aclk port.
2. Make sure the active-Low reset signal is connected to the s_axi4_aresetn port. The reset should be de-activated to make sure the core is in working condition.
3. All the registers should be accessed with a single AXI transaction and at word boundary.
4. The DTR and DRR FIFO can be accessed using a single transaction or a burst FIXED transaction.
5. The AXI4 transactions are converted in the bus2ip_* signal transactions.
6. For each SPI transaction, it is necessary to have data beats are available in DTR FIFO. The SPI transactions are enabled only when the SPICR register is configured, and the slave register should be updated to select a particular slave. The SPI transactions can be observed on SPI interface like Slave Select, SPI clock, IO0, and IO1.
7. The Slave Select line must be asserted for any SPI transaction.