Customizing and Generating the Core - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

This section includes information about using Xilinx® tools to customize and generate the core in the Vivado®Design Suite.

If you are customizing and generating the core in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 5] for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value you can run the validate_bd_design command in the Tcl Console.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

1.Select the IP from the Vivado IP catalog.

2.Double-click the selected IP, or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 1] and the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 6].

Note:   Figure in this chapter is an illustration of the Vivado IDE. This layout might vary from the current version.

This Figure shows the AXI Quad SPI Vivado Integrated Design Environment (IDE) screen.

Figure 4-1:      AXI Quad SPI Vivado IDE Screen

X-Ref Target - Figure 4-1