Write DQS-to-DQ Centering (Complex) - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English
Note: The calibration step is only enabled for the first rank in a multi-rank system. This calibration stage is skipped for data rates at or below 2,133 Mbps. At these data rates, the data eye is wide enough that prior calibration stages provide adequate DQS centering.

For the same reasons as described in the Read DQS Centering (Complex), a complex data pattern is used on the write path to adjust the Write DQS-to-DQ alignment. The same steps as detailed in the Write DQS-to-DQ Centering are repeated just with a complex data pattern.