DDR4 Pinout for 2x Component Interfaces (Non-Flipped) - 1.1 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.1 LogiCORE IP Product Guide (PG313)
Document ID
PG313
Release Date
2024-08-09
Version
1.1 English

The DDRMC can also be configured as two independent DDR interfaces of 16, 24, or 32 data bits each. The non-flipped 2x component pinout configurations are included in this section.

Nibble utilization for 2x32 interface using SDP, DDP (2 Ranks) or 3DS components in the non-flipped configuration is shown in the following figure. DQL and DQR indicate data nibbles for the left and right interfaces respectively, ACL and ACR indicate Address/Command/Control nibbles for the left and right interfaces respectively, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals. For a 1x32 interface all nibbles in the second Bank and nibbles 2, 3, 6, and 7 in the third Bank would be free.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 1. Nibble Utilization for 2x32 Interface using SDP, DDP (2 Rank), or 3DS Components (Non-Flipped)

Nibble utilization for 2x16 interface using SDP, DDP (2 Ranks) or 3DS components in the non-flipped configuration is shown in the following figure. DQL and DQR indicate data nibbles for the left and right interfaces respectively, ACL and ACR indicate Address/Command/Control nibbles for the left and right interfaces respectively, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals. For a 1x16 interface all nibbles in the second Bank would be free in addition to the free nibbles in the third Bank.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 2. Nibble Utilization for 2x16 Interface using SDP, DDP (2 Rank) or 3DS Components (Non-Flipped)

Nibble utilization for 2x24 interface using SDP, DDP (2 Ranks) or 3DS components in the non-flipped configuration is shown in the following figure. DQL and DQR indicate data nibbles for the left and right interfaces respectively, ACL and ACR indicate Address/Command/Control nibbles for the left and right interfaces respectively, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals. For a 1x24 interface all nibbles in the second Bank and nibbles 2 and 3 in addition to nibbles 4, 5, 6, and 7 in the third bank would be free.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 3. Nibble Utilization for 2x24 Interface using SDP, DDP (2 Rank) or 3DS Components (Non-Flipped)