Coherency - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
Release Date
1.0 English

The HBM Controller will check for any pending write commands that overlap the address range required by a new read or write transaction. If one exists, the new transaction will be held until the prior command has completed. The same will occur for pending reads if ECC error write back is enabled.