PHY - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

Each HBM controller has a dedicated PHY to provide the low-level physical interface to the HBM channel. It performs training and calibration to ensure reliable operation at the memory frequency set by the user. The PHY also generates all signal sequencing with the proper timing required for the interface. Additionally, the PHY also houses a PLL which generates the appropriate clock frequency per channel as chosen by the user design.